1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having different metal gate structures, and a method of manufacturing the same.
2. Description of the Related Art
Conventional transistor devices, such as metal-oxide-semiconductor (MOS) devices, are characterized by a gate dielectric of silicon oxide or silicon oxynitride interposed between a gate electrode and a channel region. The performance of such devices can be improved by increasing the capacitance between the gate electrode and channel region. One common method by which the capacitance has been increased is to decrease the thickness of the gate dielectric layers. However, degraded electrical characteristics can result from direct tunneling to the channel region in cases where the gate dielectric of silicon oxide or silicon oxynitride is made too thin. The result is increased leakage current and increased power consumption.
For example, consistent with increased integration of semiconductor devices and decreased feature sizes of MOS Field Effect Transistors (MOSFETs), gate lengths and underlying channel lengths are decreasing. Also, the thickness of the gate dielectric film has been decreased in order to increase capacitance between the gate and the channel, while maintaining the operational characteristics of a transistor. However, the typical gate dielectric film, composed of silicon oxide or silicon oxide nitride, has physical limitations related to thickness due to electrical properties, so reduced thickness may compromise reliability of the gate dielectric film. As stated above, an excessively thin silicon oxide film increases a direct tunneling current and thus the leakage current between the gate and the channel region, as well as electrical dissipation. Thus, reducing the thickness of a gate dielectric film formed from silicon oxide or silicon oxide nitride is limited.
Accordingly, methods have been sought to reduce leakage current while achieving a high gate capacitance. One method investigated by the industry is the use of materials having a high dielectric constant (high-k or high-∈) for the gate dielectric layer. Generally, gate capacitance (C) is proportional to permittivity (∈) and inversely proportional to thickness (t) (i.e., C=∈A/t, where A is a constant). Thus, an increase in thickness (t) (e.g., to 40 angstroms or more) for reducing leakage current can be offset by high permittivity (∈).
However, the use of high-k dielectrics for gate dielectric layers suffers drawbacks. This is at least partly because high dielectric materials contain a greater number of bulk traps and interface traps than thermally grown silicon oxides. These traps adversely affect the threshold voltage (Vt) characteristics of PMOS and NMOS devices. As a result, various methods of channel engineering, such as ion implantation, have been proposed in an effort to realize a target threshold voltage for devices utilizing a high-k material as a gate dielectric layer. However, such methods also cause problems such as an increase in drain induced barrier lowering (DIBL) and a decrease in a drain-to-source breakdown voltage (BVDS). Furthermore, the n-channel MOSFETs and p-channel MOSFETs of CMOS transistors generally require different gate dielectric threshold voltage characteristics, thus limiting the effective use of channel engineering techniques.
Much research is being concentrated on high-k material, which decreases the leakage current between the gate electrode and the channel region, while maintaining a thin equivalent oxide film thickness, to replace the typical silicon oxide or silicon oxide nitride. When a high-k material is used in the gate dielectric film of a MOSFET semiconductor device, electron mobility in the channel region of the semiconductor substrate under the gate dielectric film decreases, due to the bulk traps and the interface traps in the interface of the semiconductor substrate with the gate dielectric film. Moreover, the threshold voltage Vt is excessively high compared with the conventional gate dielectric film composed of silicon oxide or silicon oxide nitride. More particularly, when a gate electrode composed of a polysilicon film is formed on the gate high-k dielectric film, a gate depletion phenomenon and diffusion of dopant from the gate electrode to the gate dielectric film degrade the reliability of the semiconductor device.